In a layout design of a large-scale integrated circuit such as LSI (Large Scale Integration) or the like, a method to reduce the design period by using a hierarchical layout design is used widely. The hierarchical layout design is a method in which a chip is divided into a design unit called a macro and layout processing of each macro is carried out in a parallel way. The macro is also generally called a block or a macro block.
In the above-mentioned hierarchical layout design, a top-down oriented processing procedure like following is widely used.
First, the hierarchic structure of data of a LSI chip is determined.
Then, the position and the size of macros on the LSI chip, and the terminal positions of macros are determined (floor planning processing).
Finally, top-layout processing (i.e., wiring processing between macros), and layout processing and wiring processing in macros are carried out according to the terminal positions determined.
In such a layout design of LSI, the terminal positions of macros are determined so that a wiring route between macros may become shortest based on the size of each macro and connection relation and relative position relation between each macro.
For example, related technology of hierarchical layout design is described in Japanese Patent Application Publication No. 2005-147324.
The automatic alignment/wiring processing method described on this patent application (document 1) has a step in which the terminal positions of macros are re-determined with reference to the result of layout wiring within each of the macros which is obtained by performing hierarchical layout design mentioned above.
This automatic alignment/wiring processing method enables to reduce a roundabout of wiring between macros by carrying out this step.
Further, related technology of layout design is disclosed in Japanese Patent Application Publication No. 2007-305642.
The layout design method indicated on this patent application (document 2) has a step in which an order of connections of scan flip-flops is determined in consideration of scan path length and a step in which nodes between scan paths are exchanged.
This layout design method enables to reduce the total scan path length by carrying out these steps.
A specific example of the related technology described above will be explained using FIG. 25 and FIG. 26.
FIG. 25 indicates a scan path connection order and terminal positions in a layout after performing floor planning of a LSI.
Macros A, B, C and D that are targets of layout design of the LSI are arranged in the LSI.
Scan-in external terminal SI and scan-out external terminal SO of the LSI are arranged on the periphery of the LSI.
Each of macros A-D also includes scan-in terminals SIA-SID and scan-out terminals SOA-SOD respectively.
Scan-in terminal SIA/scan-out terminal SOA, scan-in terminal SIB/scan-out terminal SOB, scan-in terminal SIC/scan-out terminal SOC and scan-in terminal SID/scan-out terminal SOD are arranged on the peripheries of macro A, macro B, macro C and macro D respectively.
The scan path connection order is determined at the stage of logic design before performing floor planning.
At this occasion, the scan-in terminal of each macro is connected to only one terminal that is the scan-in external terminal or one of the scan-out terminals of different macros.
Similarly, a scan-out terminal is connected to only one terminal that is the scan-out external terminal or one of the scan-in terminals of different macros.
In the example of FIG. 25, the scan path is connected in order of macro C->macro D->macro A->macro B->scan-out external terminal SO, with scan-in external terminal SI being the starting point.
Incidentally, in the following description, for example, when the scan path connection order between macros is scan-in external terminal SI->macro C->macro D->macro A->macro B->scan-out external terminal SO, it is expressed as SI-C-D-A-B-SO.
Here, like other terminals, the positions of scan-in terminals SIA, SIB, SIC and SID and scan-out terminals SOA, SOB, SOC and SOD of the respective macros are arranged in positions where an each of distances between terminals becomes shortest.
Next, a layout after performing scan re-routing processing based on the floor plan of FIG. 25 is shown in FIG. 26.
A scan path is a path in which, as their own nature, all shift registers and all macros including shift registers only have to be connected like a continuous line drawn by a single stroke of a brush without lifting it from a paper. Thus, in many cases, there are no restrictions in particular about an order of their connections.
In such cases, it is possible to change the scan path connection order (scan re-routing) in consideration of the arrangement positions of macro terminals and shift registers that have been determined so that the total wiring length of the scan path may become shorter. For this reason, automated re-routing processing is generally performed.
By re-routing processing, connections of the scan path are made in order of SI-A-B-C-D-SO as shown in FIG. 26.
This is the most suitable scan path connection order in this layout and is the optimal solution of the total wiring length of the scan path.